Digital signature algorithms play a vital role in network security infrastructure. The majority of current digital signature schemes rely on RSA and ECC. However, with the rapid advancement of quantum computing, traditional public-key cryptographic schemes face increasing security risks. As a result, researching and deploying cryptographic schemes capable of resisting quantum attacks has become a critical research direction. Following multiple rounds of evaluation and analysis, National Institute of Standards and Technology (NIST) announced the post-quantum digital signature standard ML-DSA in August 2024, with Dilithium as its core algorithm. In light of the high-dimensional polynomial matrix operations characteristic of Dilithium, this paper proposes various optimization strategies based on the FPGA platform. These include multifunctional systolic array operation units with configurable parameters, dedicated polynomial parallel sampling modules, reconfigurable storage units designed for multiple parameter sets, and high-parallelism timing state machines tailored for complex multi-module architectures. These optimizations aim to overcome performance bottlenecks and achieve enhanced signature operation efficiency, ultimately realizing a digital signature hardware architecture that supports three security levels simultaneously. The proposed hardware architecture is deployed and evaluated on the Xilinx Artix-7 FPGA platform and compared against existing implementations. The results demonstrate that the proposed design achieves improvements in signature operation efficiency by factors of 7.4, 8.3, and 5.6 across the three security levels, respectively. This advancement provides a robust performance foundation for quantum-resistant digital signature applications and offers valuable insights for the engineering and practical deployment of lattice cryptographic schemes.